AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Guia do Utilizador descarregar pdf (Página 17)

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 17

UG197 (v1.5) July 22, 2009

Chapter 2

Integrated Endpoint Block Functionality

Summary

This chapter presents information on the architecture and functionality of the Virtex-5

FPGA Integrated Endpoint block. The sections include:

• “Architecture Overview”

• “Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions”

• “Registers”

Architecture Overview

The PCI Express protocol is divided into three layers: the Transaction Layer, the Data Link

Layer, and the Physical Layer. These three layers interact with the Configuration Space.

The Virtex-5 FPGA Integrated Endpoint block (Figure 2-1) provides the full functionality

of the Transaction Layer, the Data Link Layer, the Physical Layer, and the Configuration

Space as per the PCI Express Base 1.1 Specification.

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