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100 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Appendix A: Integrated Endpoint Block Attributes

BAR1ADDRWIDTH

Integer Specifies BAR 1 address width. Valid settings are:

0: 32 bits wide

1: 64 bits wide

When 64-bit addressing is selected, the BAR

occupies both the BAR1 and BAR2 registers.

BAR2ADDRWIDTH

Integer Specifies BAR 2 address width. Valid settings are:

0: 32 bits wide

1: 64 bits wide

When 64-bit addressing is selected, the BAR

occupies both the BAR2 and BAR3 registers.

BAR3ADDRWIDTH

Integer Specifies BAR 3 address width. Valid settings are:

0: 32 bits wide

1: 64 bits wide

When 64-bit addressing is selected, the BAR

occupies both the BAR3 and BAR4 registers.

BAR4ADDRWIDTH

Integer Specifies BAR 4 address width. Valid settings are:

0: 32 bits wide

1: 64 bits wide

When 64-bit addressing is selected, the BAR

occupies both the BAR4 and BAR5 registers.

Because BAR5 must always be 32-bits wide, there is

no BAR5ADDRWIDTH attribute.

BAR0PREFETCHABLE

Boolean Specifies BAR 0 memory region is prefetchable.

Valid settings are:

TRUE: prefetchable

FALSE: not prefetchable

BAR1PREFETCHABLE

Boolean Specifies BAR 1 memory region is prefetchable.

Valid settings are:

TRUE: prefetchable

FALSE: not prefetchable

BAR2PREFETCHABLE

Boolean Specifies BAR 2 memory region is prefetchable.

Valid settings are:

TRUE: prefetchable

FALSE: not prefetchable

BAR3PREFETCHABLE

Boolean Specifies BAR 3 memory region is prefetchable.

Valid settings are:

TRUE: prefetchable

FALSE: not prefetchable

BAR4PREFETCHABLE

Boolean Specifies BAR 4 memory region is prefetchable.

Valid settings are:

TRUE: prefetchable

FALSE: not prefetchable

Table A-7: Integrated Endpoint Block Attributes (Continued)

Attribute Name Type Description

1 2 ... 95 96 97 98 99 100 101 102 103 104 105 ... 119 120

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