AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Guia do Utilizador descarregar pdf (Página 1)

RVirtex-5 FPGAIntegrated Endpoint Block for PCI Express DesignsUser GuideUG197 (v1.5) July 22, 2009

10 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Preface: About This GuideRattributes are all set through the CORE G

Página 3 - Revision History

100 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRBAR1ADDRWIDTHInte

Página 4 - VC1*, LOWPRIORITYVCCOUNT

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 101UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRBAR5PREFETCHABLEBoolean Speci

Página 5 - Table of Contents

102 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRXPDEVICEPORTTYPE4

Página 6

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 103UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRPMCAPABILITYDSIBoolean Device

Página 7

104 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRMSICAPABILITYMULT

Página 8

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 105UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRLINKSTATUSSLOTCLOCKCONFIGBool

Página 9 - About This Guide

106 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRPBCAPABILITYDW0DA

Página 10 - Additional Documentation

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 107UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRAERBASEPTR12-bit Hex Location

Página 11 - Typographical Conventions

108 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesR

Página 12 - Preface: About This Guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 109UG197 (v1.5) July 22, 2009RGlossaryClick on a letter, or scroll down to view the entire glos

Página 13 - Block Overview

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 11UG197 (v1.5) July 22, 2009Additional Support ResourcesR• Virtex-5 FPGA System Monitor User Gu

Página 14

110 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RBBARBase Address Register.BeatA clock cycle where both the source

Página 15 - Use Models

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 111UG197 (v1.5) July 22, 2009RDData Link LayerThe middle layer of the PCI Express architecture,

Página 16

112 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RFunctionA logical function corresponding to a PCI function config

Página 17 - Chapter 2

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 113UG197 (v1.5) July 22, 2009RLLaneA set of differentially driven signal lines, one for each di

Página 18 - Transaction Layer

114 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009ROOrdered setThe sequences of multiples of four characters startin

Página 19 - Physical Layer

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 115UG197 (v1.5) July 22, 2009RSSidebandA signal that is implemented with its own wire. Communic

Página 20 - Physical Layer Lane Module

116 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Rmultiple virtual channels. There is no correspondence between the

Página 21 - Clock Frequency

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 117UG197 (v1.5) July 22, 2009AACTIVELANESIN attribute 24, 58, 77, 98AERBASEPTR attribute 94,

Página 22 - Endpoint Block

118 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RL0MACRXL0SSTATE port 45L0MSIENABLE0 port 50L0MSIREQUEST0 bus 5

Página 23

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 119UG197 (v1.5) July 22, 2009RNext Pointer register 55PPARITYERRORRESPONSE port 52PBBASEPTR a

Página 24

12 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Preface: About This GuideR

Página 25

120 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RTTLRAMREADLATENCY attribute 57, 98TLRAMREADLATENCY port 32TLRAM

Página 26

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 13UG197 (v1.5) July 22, 2009RChapter 1Virtex-5 FPGA Integrated Endpoint Block OverviewSummaryTh

Página 27

14 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 1: Virtex-5 FPGA Integrated Endpoint Block OverviewRVirtex-

Página 28 - Transmit

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 15UG197 (v1.5) July 22, 2009Memory RequirementsRMemory RequirementsThere are three buffers that

Página 29 - Transmit Framing

16 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 1: Virtex-5 FPGA Integrated Endpoint Block OverviewR

Página 30 - Transmit Handshake

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 17UG197 (v1.5) July 22, 2009RChapter 2Integrated Endpoint Block FunctionalitySummaryThis chapte

Página 31 - UG197_c2_04_030607

18 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRTransaction Laye

Página 32 - Receive Handshake

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 19UG197 (v1.5) July 22, 2009Architecture OverviewRThe PCI Express protocol supports four types

Página 33

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com UG197 (v1.5) July 22, 2009Xilinx is disclosing this user guide, manual, release note, and/or sp

Página 34 - UG197_c2_06_111906

20 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR• Link initializ

Página 35

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 21UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRVirt

Página 36

22 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRWhen the frequen

Página 37 - Management Interface

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 23UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRRese

Página 38 - UG197_c2_08_082406

24 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRDuring FPGA conf

Página 39

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 25UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRThe

Página 40 - Block RAM Interface

26 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRCRMURSTNInput co

Página 41 - Retry Buffer Size

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 27UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRCRMD

Página 42 - Transceiver Interface

28 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRTransaction Laye

Página 43

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 29UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRChan

Página 44

UG197 (v1.5) July 22, 2009 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockRevision HistoryThe following table shows the revision history for th

Página 45 - Power Management Interface

30 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRFraming ErrorsTh

Página 46

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 31UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRAfte

Página 47

32 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRReceive FramingT

Página 48

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 33UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRWhen

Página 49

34 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRIf LLKRXDSTREQN

Página 50

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 35UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRLLKT

Página 51

36 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRLLKRXSRCRDYNOutp

Página 52

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 37UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRMana

Página 53 - Registers

38 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRperforming the f

Página 54

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 39UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRMGMT

Página 55 - Table 2-19: MSI Registers

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com UG197 (v1.5) July 22, 200909/23/08 1.4 • Removed references to Virtual Channel 1 (VC1) and mult

Página 56 - Reserved Registers

40 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRBlock RAM Interf

Página 57

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 41UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRA pi

Página 58

42 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRPortsTable 2-11,

Página 59

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 43UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRRock

Página 60

44 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRPIPETXDATAKLnOut

Página 61

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 45UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRPowe

Página 62

46 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRConfiguration an

Página 63 - Chapter 3

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 47UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRL0MA

Página 64

48 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRL0DLUPDOWN[7:0]O

Página 65 - Chapter 4

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 49UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRL0SE

Página 66 - Configuration Requests

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 5UG197 (v1.5) July 22, 2009Revision History . . . . . . . . . . . . . . . . . . . . . . . . . .

Página 67 - Transaction Ordering

50 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRL0SETCOMPLETIONT

Página 68 - Interrupt Handling

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 51UG197 (v1.5) July 22, 2009Virtex-5 FPGA Integrated Endpoint Block Interface DescriptionsRL0ST

Página 69 - INTERRUPTDISABLE output:

52 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRBUSMASTERENABLEO

Página 70 - Error Detection

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 53UG197 (v1.5) July 22, 2009RegistersRRegistersThe tables in this section describe the register

Página 71

54 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRPower Management

Página 72

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 55UG197 (v1.5) July 22, 2009RegistersRMessage Signaled Interrupt (MSI) Capability StructureTabl

Página 73

56 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityRReserved Registe

Página 74 - Error Reporting

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 57UG197 (v1.5) July 22, 2009RegistersR4012:0 RETRYRAMWRITELATENCYRW5:3 RETRYRAMREADLATENCYRW17:

Página 75

58 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR4040 Reserved3:1

Página 76 - Phantom Function Support

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 59UG197 (v1.5) July 22, 2009RegistersR4090 BAR0ADDRWIDTHRW1 BAR1ADDRWIDTHRW2 BAR2ADDRWIDTHRW3 B

Página 77 - Lane Reversal

6 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009RConfiguration and Status Interface . . . . . . . . . . . . . . . .

Página 78 - Workaround

60 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR41012:0 Reserved

Página 79

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 61UG197 (v1.5) July 22, 2009RegistersR41812:0 VC0TXFIFOLIMITC RW13 Reserved26:14 VC0TXFIFOLIM

Página 80

62 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 2: Integrated Endpoint Block FunctionalityR

Página 81

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 63UG197 (v1.5) July 22, 2009RChapter 3Designing with the Endpoint Block Plus WrapperUsers who a

Página 82

64 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 3: Designing with the Endpoint Block Plus WrapperR

Página 83

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 65UG197 (v1.5) July 22, 2009RChapter 4Integrated Endpoint Block OperationSummaryThis chapter pr

Página 84

66 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRhas transmitted. Eve

Página 85

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 67UG197 (v1.5) July 22, 2009Transaction OrderingRTransaction OrderingThe PCI Express Base Speci

Página 86

68 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRapplied to determine

Página 87

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 69UG197 (v1.5) July 22, 2009Interrupt HandlingRDisable bit in the PCI Command register is set t

Página 88

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 7UG197 (v1.5) July 22, 2009RACK Ignored When Followed by IDLE Ordered Set . . . . . . . . . . .

Página 89

70 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRError DetectionThe P

Página 90

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 71UG197 (v1.5) July 22, 2009Error DetectionRThat configuration requests obey the following rest

Página 91 - Appendix A

72 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRThat Memory Read Req

Página 92 - TOTALCREDITS attributes are

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 73UG197 (v1.5) July 22, 2009Error DetectionRThat the TC associated with each TLP is mapped to a

Página 93 - Initial Flow Control Credits

74 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRError ReportingWhile

Página 94 - Extended Capabilities

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 75UG197 (v1.5) July 22, 2009Error ReportingRTable 4-3: Error Reporting with Integrated Endpoint

Página 95

76 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRTable 4-4 summarizes

Página 96

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 77UG197 (v1.5) July 22, 2009Lane WidthRLane WidthThe maximum number of lanes supported by a des

Página 97

78 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRKnown RestrictionsTh

Página 98

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 79UG197 (v1.5) July 22, 2009Known RestrictionsR64-Packet Threshold for Completion Streaming on

Página 99

8 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009R

Página 100

80 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRHowever, if the post

Página 101

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 81UG197 (v1.5) July 22, 2009Known RestrictionsRInvalid Cycles in LLKRXPREFERREDTYPE SignalDue t

Página 102

82 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRLink Retrain Due to

Página 103

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 83UG197 (v1.5) July 22, 2009Known RestrictionsRWorkaroundTo avoid the issues listed, the user n

Página 104

84 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRAccess to Unimplemen

Página 105 - Contains the offset of

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 85UG197 (v1.5) July 22, 2009Known RestrictionsRWorkaroundThe user can work around this issue by

Página 106

86 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationRCredit Leak When Tra

Página 107

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 87UG197 (v1.5) July 22, 2009Known RestrictionsRReceipt of Back-to-Back ACK DLLPsWhenever ACKs a

Página 108 - UG197 (v1.5) July 22, 2009

88 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 4: Integrated Endpoint Block OperationR

Página 109 - Glossary

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 89UG197 (v1.5) July 22, 2009RChapter 5Simulating with the Integrated Endpoint BlockFor simulati

Página 110

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 9UG197 (v1.5) July 22, 2009RPrefaceAbout This GuideThis guide serves as a technical reference d

Página 111

90 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Chapter 5: Simulating with the Integrated Endpoint BlockR

Página 112 - Isochronous data transfer

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 91UG197 (v1.5) July 22, 2009RAppendix AIntegrated Endpoint Block AttributesSummaryThis appendix

Página 113

92 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRinterspersed with

Página 114

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 93UG197 (v1.5) July 22, 2009Initial Flow Control CreditsR The write latency attribute settings

Página 115

94 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesR• Infinite Complet

Página 116

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 95UG197 (v1.5) July 22, 2009Extended CapabilitiesRTwo linked lists are defined. The method used

Página 117

96 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRIntegrated Endpoin

Página 118

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 97UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRVC0RXFIFOBASEP13-bit Hex Base

Página 119

98 www.xilinx.com Virtex-5 FPGA Integrated Endpoint BlockUG197 (v1.5) July 22, 2009Appendix A: Integrated Endpoint Block AttributesRACTIVELANESIN8-bit

Página 120

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 99UG197 (v1.5) July 22, 2009Integrated Endpoint Block AttributesRL0SEXITLATENCYCOMCLKInteger Se