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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 13

UG197 (v1.5) July 22, 2009

Chapter 1

Virtex-5 FPGA Integrated Endpoint

Block Overview

Summary

This chapter introduces the integrated Endpoint block embedded in Virtex-5 devices. The

sections include:

• “The PCI Express Standard”

• “Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs”

• “Memory Requirements”

• “Use Models”

The PCI Express Standard

The PCI Express (PCIe®) standard is a next-generation evolution of the older PCI™ and

PCI-X™ parallel bus standards. It is a high-performance, general-purpose interconnect

architecture, designed for a wide range of computing and communications platforms. It is

a packet-based, point-to-point serial interface that is backward compatible with PCI and

PCI-X configurations, device drivers, and application software. Its faster, serial-bus

architecture with dedicated, bidirectional I/O represents a fresh architectural approach.

Table 1-1 shows the bandwidth for various lane configurations. The effective bandwidth is

lower than the raw bandwidth due to the overhead of the 8B/10B encoding and decoding

used by the protocol.

Table 1-1: PCIe Standard Bandwidth

Link Raw Bandwidth per Direction Effective Bandwidth per Direction

x1 2.5 Gb/s 2 Gb/s

x2 5 Gb/s 4 Gb/s

x4 10 Gb/s 8 Gb/s

x8 20 Gb/s 16 Gb/s

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 119 120

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