AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Guia do Utilizador Página 101

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Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 101
UG197 (v1.5) July 22, 2009
Integrated Endpoint Block Attributes
BAR5PREFETCHABLE
Boolean Specifies BAR 5 memory region is prefetchable.
Valid settings are:
TRUE: prefetchable
FALSE: not prefetchable
BAR0IOMEMN
Integer Selects Memory or I/O Space for BAR 0. Valid
settings are:
0: Memory Space
1: I/O Space
BAR1IOMEMN
Integer Selects Memory or I/O Space for BAR 1. Valid
settings are:
0: Memory Space
1: I/O Space
BAR2IOMEMN
Integer Selects Memory or I/O Space for BAR 2. Valid
settings are:
0: Memory Space
1: I/O Space
BAR3IOMEMN
Integer Selects Memory or I/O Space for BAR 3. Valid
settings are:
0: Memory Space
1: I/O Space
BAR4IOMEMN
Integer Selects Memory or I/O Space for BAR 4. Valid
settings are:
0: Memory Space
1: I/O Space
BAR5IOMEMN
Integer Selects Memory or I/O Space for BAR 5. Valid
settings are:
0: Memory Space
1: I/O Space
BAR0MASKWIDTH
6-bit Hex Specifies top bit of address range for BAR 0. Valid
settings are in the range 04h to 3Fh.
BAR1MASKWIDTH
6-bit Hex Specifies top bit of address range for BAR 1. Valid
settings are in the range 04h to 3Fh.
BAR2MASKWIDTH
6-bit Hex Specifies top bit of address range for BAR 2. Valid
settings are in the range 04h to 3Fh.
BAR3MASKWIDTH
6-bit Hex Specifies top bit of address range for BAR 3. Valid
settings are in the range 04h to 3Fh.
BAR4MASKWIDTH
6-bit Hex Specifies top bit of address range for BAR 4. Valid
settings are in the range 04h to 3Fh.
BAR5MASKWIDTH
6-bit Hex Specifies top bit of address range for BAR 5. Valid
settings are in the range 04h to 3Fh.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description
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