AMX AXT-MCP Manual do Utilizador Página 8

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PDF: OneNAND Very Large Page 34nm MCP.pdff Micron Technology, Inc., reserves the right to change products or specifications without notice.
OneNAND Very Large Page 34nm MCP - Rev. B 8/11 EN
8 ©2010 Micron Technology, Inc. All rights reserved.
OneNAND Compatible VLP 34nm + LPSDRAM, MCP
Signal descriptions
Micron Confidential and Proprietary Preliminary
D-BA[1:0]
-
Bank Select
inputs
Inputs Selects the DRAM bank to be made active.
When selecting the addresses, the device must be
enabled, the D-RAS# must be low, at VIL, the D-CAS#
and D-WE# must be high, at VIH.
D-DQ[15:0]
-
Data inputs/
outputs
Inputs/
Outputs
Output the data stored at the selected address during
a read operation, or input the data during a write
operation.
D-CLK
D-CLK#
CK
, K
D
Clock inputs
Inputs The clock signals are the master clock inputs.
All signals, except D-DQM, D-DQS and D-DQ[15:0], are
referred to the cross point of D-CLK rising edge and D-
CLK# falling edge.
D-CKE Clock Enable
input
Input When driven low, at VIL, D-CLKE is used to suspend D-
CLK, to switch the device to self refresh or power
down.
D-CLKE must be stable for at least one clock cycle.
D-CE#
E
D
Chip Enable
input
Input When driven low, at VIL, activates the memory state
machine, address buffers and decoders.
When driven high, at VIH, the device is not selected.
D-WE#
W
D
Write Enable
input
Input
Controls writing.
D-RAS#
RAS
D
Row Address
Strobe input
Input
Used in conjunction with address inputs D-A[max:0] and
D-BA[1:0] to select the starting address location prior to a
read or write.
D-CAS#
CAS
D
Column Address
Strobe input
Input
Used in conjunction with least significant address inputs
and D-BA[1:0] to select the starting column location prior
to a read or write operation.
D-DQM[1:0]
-
DQ mask enable
Inputs Masks the data read from or written to the DDR
LPSDRAM.
Each D-DQM signal corresponds to 8 data pins:
D-DQM1 is the input data mask signal for DQ15-DQ8
D-DQM0 is the input data mask signal for DQ7-DQ0
D-UDQS,
D-LDQS
-
Data read/write
strobe
Inputs/
Outputs
Can be either input or output signals and act as write
data strobe and read data strobe.
Each D-DQS signal corresponds to 8 data pins:
D-UDQS is the input data mask signal for DQ15-DQ8
D-LDQS is the input data mask signal for DQ7-DQ0
D-VDD
-
Supply voltage
Provides the power supply to the internal core of the
memory device.
It is the main power supply for all operations (read
and write).
It is recommended to power up and power down D-
VDD and D-VDDQ together to avoid conditions that
would result in data corruption.
Table 2: Signal names (Continued)
Signal
symbol
Alternate
signal
symbol Function Type Description
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