PDF: OneNAND Very Large Page 34nm MCP.pdff Micron Technology, Inc., reserves the right to change products or specifications without notice.
OneNAND Very Large Page 34nm MCP - Rev. B 8/11 EN
7 ©2010 Micron Technology, Inc. All rights reserved.
OneNAND Compatible VLP 34nm + LPSDRAM, MCP
Signal descriptions
Micron Confidential and Proprietary Preliminary
O-ADV#
L
F
Latch Enable
Input
•Indicates that the address present on O-ADQ[15:0] are
valid.
• During asynchronous read operations, O-ADV# at VIL
indicates that the addresses are valid and the
addresses are latched on O-ADV# rising edge.
• During synchronous read operations, addresses are
latched on the O-CLK rising edge while O-ADV# is
held at VIL for one clock cycle.
• When O-ADV# is at VIH, address inputs are ignored.
O-INT
-
Interrupt (open
drain output)
Output • An open drain output that notifies the host micropro-
cessor that a command is completed.
• It is high impedance after power-on. Once the IOBE
bit of the configuration register is set to “1”, the O-
INT signal is enabled and does not remain high
impedance even if O-CE# or O-OE# are disabled.
• Before issuing a command or executing an operation,
the O-INT signal must be driven busy by programming
the interrupt status to “0000h”. When the operation
is completed, O-INT goes back to ready state. The busy
and ready states are configured through the bit
INTpol (INT polarity) of the configuration register.
O-RDY
-
Ready
Output • During synchronous operations, the O-RDY indicates
that valid data available on O-ADQ[15:0].
• Activated when O-CE# is at VIL.
• High impedance after power-on.
• Enabled by setting the IOBE bit of the configuration
register to "1".
O-VDD
-
Supply voltage
– • Provides the power supply to the internal core of the
memory device.
• It is the main power supply for all operations (read,
program and erase).
O-VDDQ
-
Supply voltage
for input/output
buffers
– • Provides the power supply to the I/O pins and enables
all outputs to be powered independently from O-
VDD.
• It can be tied to O-VDD or can be used as a separate
supply.
O-VSS
-
Ground
– • It is the reference for the core supply.
• It must be connected to the system ground.
LPSDRAM
D-A[12:0]
-
Address inputs
Inputs • Selects the DRAM row or column to be made active.
• A10 determines whether read or write operation
include auto precharge cycle: if A10 is low (“0”), it is
not used; if A10 is high (“1”), it is used.
• The D-A[12:0] are latched at the cross points of D-CLK
rising edge and D-CLK# falling edge.
Table 2: Signal names (Continued)
Signal
symbol
Alternate
signal
symbol Function Type Description
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