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PDF: OneNAND Very Large Page 34nm MCP.pdff Micron Technology, Inc., reserves the right to change products or specifications without notice.

OneNAND Very Large Page 34nm MCP - Rev. B 8/11 EN

OneNAND Compatible VLP 34nm + LPSDRAM, MCP

Signal descriptions

Micron Confidential and Proprietary Preliminary

Signal descriptions

Table 2Signal names provides a brief overview of signals connected to the devices.

Table 2: Signal names

Signal

symbol

Alternate

signal

symbol Function Type Description

Not connected

internally

–

Not connected internally

Do not use

–

Do not use

OneNAND Flash memory (Mux)

O-ADQ[15:0]

Data input/

outputs or

address inputs,

command

inputs

Inputs/

Outputs

Multiplexed address/data (ADQ[15:0]) can be used for

multiple purposes:

• Address input during read operations to access the

RAM buffer and the register

• Data input during program operations

• Commands inputs

• Data output during read operations from the memory

array or from registers

• ADQ[15:0] are left floating when the device is dese-

lected or the outputs disabled.

O-CE#

Chip Enable

Input • Activates the Flash memory control logic, input

buffers, decoders and sense amplifiers.

• When O-CE# is at VIL, the device is in active mode.

• When O-CE# is at VIH, the memory is deselected, the

outputs are high impedance and the power consump-

tion is reduced to standby level.

O-OE#

Output Enable

Input

Controls data outputs during the bus read operation of

the memory.

O-WE#

Write Enable

Input

Controls the bus write operation of the memory's

command interface.

O-RP#

RST

, RP

Reset

Input • Provides a hardware reset of the memory.

• When O-RP# is at VIL, the device is in reset mode. All

blocks are in the locked state and the configuration

• When O-RP# is at VIH, the device is in normal opera-

tion. Upon exiting reset mode, the device enters asyn-

chronous read mode, but a negative transition of O-

CE# or O-ADV# is required to ensure valid data

outputs.

O-CLK

CK, K

Clock

Input • Synchronizes the memory to the system bus

frequency, during synchronous burst mode.

• The addresses are latched on the first O-CLK rising

edge when O-ADV# is at VIL.

1 2 3 4 5 6 7 8 9 10 11 ... 15 16

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