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DNA/DNR-AI-217 Simultaneous Sampling Differential Analog Input Board

Chapter 1 11

Introduction

Tel: 508-921-4600 www.ueidaq.com Vers: 4.5

Date: April 2013 DNx-AI-217 Chap1x.fm

United Electronic Industries, Inc.

nous operation of multiple layers; however if there are other layers in the system

that require synchronization using the scan clock then there are two other

options that should be considered. One is to divide the master 8x clock by eight

clock cycles using the CT-601 layer and distribute it across the system. However

if an extra layer is not an option then each individual layer can be configured to

run the ADC at maximum rate of 120KHz and the scan clock is used as a gate

that grabs one last scan received from the converters; thus synchronizing the AI-

217 using the scan clock. This way all layers are synchronized within ±1 conver-

sion cycle (8.33

µsec).

1.6.2 FIR Filter A unique feature of the AI-217 is the use of four 4-channel (i.e. 0 to 3, 4 to 7, 8

to 11, 12 to 15) FIR filters implemented on-chip in the FIR module logical block.

Each channel uses its own storage for the data and each four channels share

the same coefficients and decimation ratio. By default, all channels are set to the

same coefficients and decimation ratio by the software function call for simplicity,

and thus have the same output data rate. Coefficients and decimation ratio are

automatically selected by the software calls to an optimum value to match the

throughput. The FIR filter can either be disabled or enabled with automatic or

user-configured coefficients using software function calls. The FIR module’s

decimation ratio can also be user-configured to 0 (keep all samples) or higher.

This section discusses the configuration of the digital FIR filter found in the FIR

module logical block. This should not be confused with the FIR filters also found

in the AD7766 (as per its datasheet), or the anti-aliasing filter circuit on the front-

end of the PGA discussed much earlier.

The FIR module implements an integer-based finite-input-response filter with:

• 128-taps on the AI-217-1, for a faster response and lower group delay, or as

• 512-taps on the AI-217-803, which provides a sharper filter with less ripple.

The default filter is configured to suppress harmonics above one half of the ADC

output data rate, however, you can generate/use your own filter coefficients.

The filter operates as per standard digital FIR filter theory:

1. The newest input sample from the ADC is put into the delay line register.

2. Each sample in the delay line is multipled by the corresponding coefficient.

Accumulate all multiplied values to provide the result to the output line.

3. Shift the delay line by one sample to make room for the next input sample.

The caveats of using the FIR filter are that rippling may occur in response to

sharp edges and there is a group delay of 128/2=64 or 512/2=256 ADC samples

before the output is provided into the output buffer.

1.7 Diagnostics A standard feature available with the AI-217 is a diagnostic function called

DqAdv217GetPgaStatus(). You can call this function at any time to perform

a series of diagnostic tests of board operation. Refer the PowerDNA API

Reference Manual for a detailed description of how the function works and to the

sample code on how to use it.

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