AMX AXP-AI8 ANALOG 8-INPUT BOARD Manual do Utilizador descarregar pdf (Página 14)

DNA/DNR-AI-217 Simultaneous Sampling Differential Analog Input Board

Chapter 1 10

Introduction

Tel: 508-921-4600 www.ueidaq.com Vers: 4.5

Date: April 2013 DNx-AI-217 Chap1x.fm

United Electronic Industries, Inc.

placed into the output buffer in the same order as they are in the channel list,

however each data sample incorporates a channel number that can be used to

re-order the output buffer in software.

Using the output channel list, the PGA Access Module manages PGA

operations, stores data from each, and generates error IRQs for any error

conditions that occur. Error interrupts output from the PGA access module are

processed in the standard DNA logic.

1.6.1 A/D

Conversion

The AI-217 implements ADC converters that utilize an oversampled SAR archi-

tecture and require a clock source (mclk) that is 8x the ADC’s output data rate.

The input clock source for the ADCs is kept between 480KHz to 960KHz for the

AI-217-1; meaning that the actual data rate from the AD7766 is always 60k-120k

samples/second, which is free from aliasing because of the analog anti-alias fil-

ter mentioned previously.

To get output data rates less than 60kHz the layer’s FIR module’s decimation

unit will only keep 1 in n samples, where n is the decimation factor. The following

pseudocode shows how to calculate the master clock frequency and the deci-

mation ratio for the AI-217-1, which is useful when not using the on-layer clock:

For the AI-217-803, decimation is disabled; the maximum master clock source

(mclk) is 240kHz which gives an output data rate of 30kHz. With the AI-217-803

the user may need to supply an appropriate input anti-aliasing (low-pass) filter

on the front-end, similar to the R-C filter of the AI-217-1, if aliasing below 56kHz

is to be expected. Finally, the CJC channel is read once per decimation cycle.

Both sample rate and decimation factor are configured by your user application

through function calls listed in Chapter 3.

The AI-217 provides a special clock divider that can use 66MHz as well as fixed

21.12MHz or 25.6MHz clocks to create different frequencies used to run the

ADC; the AI-217

incorporates a programmable PLL that allows the generation

of the base frequency with 0.1% or better accuracy. Alternatively the UEI DNx-

IRIG-650 layer’s 100MHz base clock and PLL can also be used to generate a

very precise master clock signal of 480-960KHz and route it into the AI-217

ADCs. The “master” clock shall be constantly running even when conversion

results are not used because it has a long FIR filter that should stay settled (see

AD7766/AD7767 datasheet for details about the ADC). Thus, samples are

always produced, but are not stored in the output buffer until a start command or

start trigger is issued.

When multiple layers should be synchronized, the clock generated by a master

layer should be routed to the SYNC bus (e.g. SYNC1 line) and from there back

to the clock of the slave layers (CVOUT). Keeping all AI-217 layers synchro-

nized using an 8x ADC clock and hardware trigger would provide fully synchro-

// calculate decimation factor and sample rate

decratio = 1;

while (mclkrate <= (480000/8)){ // start at 60000Hz

mclkrate *= 2;

decratio *= 2;

}

1. This feature is supported on logic revision 02.10.D3 (2013). UEI Technical Support

can provide you with a field programmable update package if your logic is older. Use

PowerDNA Explorer’s Hardware Report to show logic versions for your AI-217.

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