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Chapter 7: IP Core Interfaces 7–49

Physical Layer Interface Signals

December 2013 Altera Corporation Cyclone V Hard IP for PCI Express

User Guide

1 In all figures channels and PLLs that are gray are unused.

■

1 In all figures channels and PLLs that are gray are unused.

CycloneV devices include one or two Hard IP for PCI Express IP Cores. The following

figures illustrates the placement of the Hard IP for PCIe IP cores, transceiver banks

and channels for the CycloneV devices. Note that the bottom left IP core includes the

CvP functionality.

In the following figure, the Hard IP for PCI Express uses channel 1 and channel 2 of

GXB_L0 and channel 4 and channel 5 of GXB_L1. Devices with a single Hard IP for

PCIe IP Core only include the bottom left core.

Figure 7–1. Channel and Hard IP for PCI Express IP Core Locations in CycloneGX and GT Devices

GXB_L1

GXB_L0

Transceiver

Bank Names

PCIe Hard IP

with CvP

Ch 2

Ch 1

Ch 0

Ch 5

Ch 4

Ch 3

6 Ch

PCIe Hard IP

1 2 ... 142 143 144 145 146 147 148 149 150 151 152 ... 287 288

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AMX DESIGN XPRESS V 1.5 - PROGRAMMER GUIDE Guia do Utilizador Página 147